The modules below take a 8-bit binary number on the number input and converts that number into three 4-bit BCD numbers, one for each decimal place. Product Categories: FPGAs (Field Programmable Gate Array)įPGA XC4000XLA Family 28K Gates 2432 Cells 263MHz 0.35um Technology 3. The Verilog and VHDL code below is for an 8-bit binary to BCD decoder that gives and ones, tens and hundreds decimal place output for driving a display or other device.

In the results this time you can see the counter variable in binary and also in unsigned decimal counting up to 1001 (binary) and 9 (decimal), then returning back to 0, giving the decimal counter.įPGA XC4000E Family 3K Gates 238 Cells 0.35um Technology 5V 100-Pin PQFP EP In a similar manner we can implement a BCD counter in Verilog using the code given here:Ģ4 counter_output <= #1 counter_output + 1 Īnd test it using the same basic counter test bench created for the simple counter, giving the simulation results as shown in Figure 24.7. The only change is that the counter has an extra check to reset when the value of the count variable is greater than 9 (the counter range is 0 to 9).ġ1 output : out std_logic_vector((n−1) downto 0)ġ8 variable count : unsigned((n−1) downto 0) The VHDL for a simple BCD counter is given in the following listing. The VHDL for a BCD counter is very similar to that of a basic binary counter except that the maximum value is 10 (hexadecimal A) instead of 15 (hexadecimal F).

This counter is often used for decimal displays and other human interface hardware. The BCD (Binary Coded Decimal) counter is simply a counter that resets when the decimal value 10 is reached instead of the normal 15 for a 4-bit binary counter.

Binary to bcd verilog